1. Field of the Invention
The present invention relates to a flash memory erase operation controller and to a method for controlling a flash memory erase operation, and more particularly it relates to a high-speed flash memory that eliminates malfunctioning by reliably discharging a residual charge remaining in a memory cell in a short period of time.
2. Related Art
Flash memories have been known in the past, and a method of erasing a flash memory of the past, such as the substrate erase method, is shown in the equivalent circuit diagram and structural cross-sectional view of FIG. 14 and FIG. 15.
Specifically, in this substrate erase method, the gate voltage Vg is set to a negative voltage Vneg (for example, xe2x88x928 V), the source voltage Vs and drain voltage Vd being left in the open state, and the substrate voltage Vb being set to a positive voltage Ves (for example, xe2x88x928 V), so that floating electrons accumulated on the floating gate 158 are discharged to the substrate, thereby achieving erasure.
This memory cell is formed by a forming an N well 152 on a P-type substrate 151 and forming a P well 153 electrically isolated from the P-type substrate 151, forming an N-type diffusion layer 154 on the N well 152 for the purpose of applying a voltage to the N well 152, and forming a P-type well diffusion layer 155 on the P well 153 for the purpose of applying a voltage to the P well 153.
Additionally, in this memory cell an n-type source diffusion layer 156 and an N-type drain diffusion layer 157 are formed on the P well 153, and a floating gate 158 and control gate 159 are formed.
Each of the diffusion layers 156 and 157 are separated by a field insulation film 160.
By adopting the above-noted structure, it is possible to use the substrate erase method, in which a positive voltage is applied to a substrate part of the memory cell.
FIG. 9 is a block diagram showing an example of the structure in a flash memory of using the above-described substrate erase memory, and in the operation of this device, a gate of the memory cell MC1 is controlled by a row decoder 1 via a row line WL, and when erasing is to be performed, an output voltage Vneg of a negative voltage boosting circuit 2 is supplied to the gate of the memory cell via the row decoder 1.
At times other than when an erase operation is performed, an N-type MOSFET MN6 is provided at the connection node with the negative voltage Vneg for the purpose of setting a voltage of Vneg, which is the output of the negative voltage boosting circuit 2, to the ground potential.
The drain CBL of the memory cell MC1 is connected to the read /write circuit 3, the source CSL of the memory cell is set to the ground potential GND by setting the N-type MOSFET MN2 to the conducting state at the time of reading or writing, and the source CSL of the memory cell is placed in the open state by setting the N-type MOSFET MN2. to the non-conducting state when an erase is performed.
Additionally, the substrate CWL of the memory cell MC1 is set to the ground potential GND by setting the N-type MOSFET MN4 to the conducting state at the time of reading or writing, and the substrate CWL of the memory cell is supplied with the output Ves of the positive voltage boosting circuit 4 when an erase is performed.
The N-type MOSFETs MN3, MN5, MN1, and MN7 are provided for the purpose of discharging the electrical charge on each one of the source CSL of the memory cell MC1, the substrate CWL, a drain CBL, and the gate WL.
As noted above, the erase operation for each memory cell MC1 of this flash memory is performed in unites of sectors, and because the capacity of the memory cells is large (512 Kbits), the parasitic capacitance is extremely large, so that to prevent a large amount of noise being generated at the ground potential GND when a sudden discharging is done, the N-type MOSFETs MN3, MN5, MN1, and MN7 are disposed so as to adjust the transistor capacity.
The erase operation in this flash memory is described. below, with references being made to the voltage waveform diagrams of FIG. 10 and FIG. 11.
FIG. 10 is a voltage waveform diagram showing the operation at the start of an erase operation.
At time T1, the signals CSG, CWG, CWP, and XDP all change from the high level to the low level, resulting in setting the N-type MOSFETs MN2, MN4, and MN6 to the non-conducting state and setting the P-type MOSFET MP1 to the conducting state.
After time T1, by the start of the operation of the positive voltage boosting circuit and the negative voltage boosting circuit the positive erase voltage Ves rises from Vcc up to, for example, 8 V, and the negative erase voltage Vneg rises from the ground potential GND to, for example, xe2x88x928 V, whereupon the memory cell is subjected to an erase operation by the gate WL also changing to xe2x88x928 V.
When this occurs, CSL and CBL, which are the source and drain of the memory cell, are in the open state, with the PN junctions between the substrate of the memory cell and the source and the drain forward biased, so that current flow into the source and drain from the substrate, the resulting voltage being approximately 7.4 V, which is approximately 0.6 V lower than the forward breakdown voltage of the PN junction.
FIG. 11 is a voltage waveform diagram showing the end of the erase operation.
Specifically, at time T3 the signal CWP changes from the low level to 8 V, which is the same as the Ves, so that the P-type MOSFET MP1 changes to the non-conducting state, thereby cutting off the current path between the positive erase voltage Ves and the substrate CWL of the memory cell.
The negative voltage boosting circuit stops operating at the time T3.
Simultaneously with the above, the signals DISP and DISN change from the low level to the high, level, resulting in the N-type MOSFETs MN1, MN3, MN5, and MN7 all going into the conducting state, which causes the negative voltage and positive voltage applied when erasing to discharge to the ground potential GND, and at time T4, at the time when the discharging has been completed, the operation of the positive voltage boosting circuit also stops, so that the positive erase voltage Ves stops the erase operation at Vcc.
In a flash memory of the past as described above, because the discharging of the various connection nodes (gate, source, drain, and substrate) of the memory cell at the completion of the erase operation is controlled separately, for example, it is extremely difficult to adjust the transistor capacity for each discharging, and various types of noise is generated.
For example, FIG. 12 shows an example in which the discharging capacity of the N-type MOSFETs MN7 to discharge the negative erase voltage Vneg is larger than that of the N-type MOSFETs MN1, MN3, and MN5.
The negative erase voltage Vneg transitions rapidly from xe2x88x928 V to the ground potential GND at the time T3, this causing a shift of the ground potential GND within the memory cell in the negative voltage direction, leading to the possible blocking of the operation of the peripheral circuitry, and also because the negative erase voltage Vneg is capacitively coupled to the source, the substrate, and the drain of the memory cell via the gate capacitance of the memory cell, the potentials of the source, substrate, and drain of the memory cell are pulled upward, so that excessive stress is placed on the transistors connected to these nodes.
FIG. 13 shows an example in which the discharging capacities of the N-type MOSFETs MN1, MN3, and MN5 which discharge the positive high-voltage terminal are greater than that of the N-type MOSFET MN7, which discharges the negative erase voltage Vneg.
The substrate CWL, source CSL, and drain CBL which are at a high positive voltage suddenly transition from 8 V to the ground potential GND at the time T3, causing the ground potential GND within the semiconductor memory to change in the positive voltage direction, leading to possibility of blocking the operation of the peripheral circuitry. Additionally, according to the same principle as described with regard to FIG. 12, the negative erase voltage Vneg is pushed downward, so that excessive stress is placed on transistors connected to this node.
Additionally, although not shown in the drawings, in also the discharging of the source, substrate, and drain of memory cell, which are also raised to a high positive voltage, the alignment of the voltage changes when this discharging is performed is extremely difficult, requiring estimation of the parasitic capacitance at each node and adjustment of the transistor capacities for each discharge.
A cause of the above-noted problems is that, when electrical charges at various nodes in the memory cell (gate, source, drain, and substrate) at the time of erasing are discharged, the control of discharging at the various nodes is performed separately.
There is a method of performing erasing of a flash memory by applying positive and negative voltages to different nodes of a memory cell. For example, as disclosed in Japanese unexamined patent publication (KOKAI) No.6-275842, in a substrate erase method, a negative voltage is applied to a gate of a memory cell and a positive voltage is applied to the substrate part of the memory cell, to perform erasing, and in U.S. Pat. No. 5,077,691, there is. a gate-source erase method in which a negative voltage is applied to a gate of a memory cell and positive voltage is applied to a source of the memory cell.
For example, in recent 32-Mbit flash memories using the substrate erase method, using 512 Kbits as the unit for erasing, when an erase is performed a negative voltage is applied to all gates of memory cells for 512 Kbits, and a positive voltage is applied to the substrate to perform the erasing operation.
The negative voltage and positive voltage at the time of erasing are generated by a boosting circuit within the semiconductor memory and supplied to the memory cells. However, because the step-up capacity of the boosting circuit is not that great, there is a relative slow change in the voltage, taking from several microseconds to several tens of microseconds, occurs at the gates of the memory cells and the substrate at the start of the erase operation, and at the end of the erase operation the electrical charges accumulated on the gates of the memory cells and the substrate are discharged via a MOSFET to the ground potential, so that unless the MOSFET is designed properly there is the problem of losing operation of the internal circuitry due to a shift in the ground potential within the semiconductor memory.
That is, in an erasing operation of the past, the major concern was with regard to the discharging of a positive electrical charge. If discharging of a negative electrical charge is insufficient, however, the potential on the substrate tends to shift, this being accompanied by the danger that the substrate potential will be fixed at a negative voltage, in which case the operation of the flash memory itself is abnormal.
In the Japanese unexamined patent publication (KOKAI) No.10-214491, there is an erase method for a flash memory, in which the basic technical concept is that of a channel erase method, in which a negative voltage is applied to a gate and a positive voltage greater than Vcc is externally applied to the channel, along with the essential condition that source and drain of the memory cell are connected to the ground potential via a low-resistance current path. This reference, however, does not disclose a method of erasing, such as in the present invention, in which at least one of the gate part, the source part, the drain part, and the substrate is directly connected.
In Japanese unexamined patent publication (KOKAI) No.5-174588, there is disclosure of applying to the source and drain of a memory cell an electrical charge at or above the ground potential, and applying a negative potential below the ground potential to the gate in order to perform an erase operation. In Japanese unexamined patent publication (KOKAI) No.10-172293, there is an erasing method having a first erase mode with having a first step of setting the drain voltage of a memory cell to a voltage lower than the source voltage, a second step of setting the drain of the memory cell to the open state, and a third step of applying a positive voltage to the source of the memory cell, and a second erase mode having a fourth step of setting the gate of the memory cell to the ground potential and a fifth step of setting the source of the memory cell to the ground potential. That reference, however, does not disclose a method of erasing, such as in the present invention, in which at least one of the gate part, the source part, the drain part, and the substrate is directly connected.
Additionally, in Japanese unexamined patent publication (KOKAI) No.10-275484, there is a method of disposing a dummy memory cell at each memory cell, wherein when performing a write operation before applying a positive voltage to a gate the dummy memory cell is set to the on state to make the potential on the data line and the source line the same. That method, however, does not disclose a method of erasing, such as in the present invention, in which at least one of the gate part, the source part, the drain part, and the substrate is directly connected.
Accordingly, it is an object of the present invention to improve on the above-described drawbacks in the prior art, by providing a flash memory erase operation control method and flash memory erase operation controller which reliably causes surely discharging of a residual electrical charge in a memory cell in a short period of time, thereby eliminating faulty operation and enabling application to high-speed flash memories.
To achieve the above-noted objects, the present invention adopts. the following basic technical constitution.
Specifically, a first aspect of the present invention is a flash memory erase operation controller, which has a common discharging circuit part that makes a direct electrical connection between the gate part and at least one of the source part, the drain part, and the substrate part making up a memory cell, during the erase operation, and a second aspect of the present invention is a method for controlling an erase operation in a flash memory, whereby when performing an erase operation in a flash memory circuit, at least one of the source part, the drain part, and the substrate part making up a memory cell is directly connected electrically to the gate part during the erase operation.
By adopting the above-noted technical constitutions, a method for controlling an erase operation in a flash memory and a flash memory erase operation controller according to the present invention reliably discharge a residual electrical charge in a memory cell completely in a short period of time, thereby eliminating faulty operation and providing a method and controller for erase operation that is suitable for application to a high-speed flash memory.
Specifically, a basic technical feature of a method for controlling an erase operation in a flash memory and a flash memory erase operation controller according to the present invention is that a negative voltage (Vneg) applied to the gate of a memory cell, and the nodes of the source (CSL), the substrate (CWL), and the drain (CBL) are each connected to a common discharge node DISCOM, via the N-type MOSFETs MDN3 to MDN6, respectively,and further that an N-type MOSFET MDN7 is provided between the connection of the common discharge node DISCOM and the ground potential, so that the potentials at the various nodes of the memory cell are discharged via the common discharge node DISCOM.